The present invention relates generally to a ballast circuit for a gas discharge lamp. More particularly, this invention relates to increasing the d.c. bus charging rate in a power factor correction circuit of the ballast circuit for a gas discharge lamp during a startup period.
A prior art circuit for supplying a load with bi-directional current includes a series half-bridge converter comprising a pair of series-connected switches that are alternately switched xe2x80x9conxe2x80x9d to achieve bi-directional current flow through the load.
In order to improve the power factor of the load, the prior art power supply circuit incorporates a boost converter which receives rectified, or d.c., voltage from a full-wave rectifier, which, in turn, is supplied with a.c. voltage and current. The boost converter generates a voltage boosted above the input d.c. voltage on a capacitor of the boost converter (xe2x80x9cthe boost capacitorxe2x80x9d), which supplies the d.c. bus voltage for powering the mentioned series half-bridge converter. The prior art boost converter includes a dedicated switch (xe2x80x9cthe boost switchxe2x80x9d) which repetitively connects an inductor of the boost converter (xe2x80x9cthe boost inductorxe2x80x9d) to ground and thereby causes current flow in the inductor, and hence energy storage in such inductor. The energy stored in the boost inductor is then directed to the boost capacitor, to maintain a desired bus voltage on such capacitor.
In the operation of the prior art boost converter, the energy stored in the boost inductor is discharged into the boost capacitor prior to the boost switch again connecting the boost inductor to ground. Operation of the boost converter as described, i.e. with complete energy discharge of the boost inductor, is known as operation in the discontinuous mode of energy storage. Prior art circuits may also operate in the continuous mode of energy storage, wherein the inductor is not to fully discharge. This allows the circuit to keep some stored energy.
Unfortunately, boost converters incorporating power factor correction use a method of limiting the current through the boost switch to control the d.c. bus voltage. The maximum value of current through the boost switch is determined by the steady-state operation of the converter under full load conditions. Initially, when power is first applied, the d.c. bus is uncharged. The rate at which the d.c. bus charges is determined by the maximum value of current allowed by the controller. If the charging rate can be increased during the initial charging of the bus, the d.c. bus voltage will reach its steady-state value sooner. This is desirable in applications where the power supply circuit is a ballast circuit and the boost converter (i.e., power factor correction circuit) supplies the d.c. bus to a plurality of inverters, each of which powers a gas discharge lamp.
Since the time it takes the load current to reach its steady-state value is proportional to the d.c. bus voltage, it is desirable for the d.c. bus voltage to reach its steady-state value sooner than in existing boost converters (i.e., power factor correction circuits).
In an embodiment of the present invention, a ballast circuit comprises a bridge rectifier, a power factor correction circuit operationally coupled to the bridge rectifier, wherein the power factor correction circuit sources a d.c. bus to subsequent ballast circuit components and provides a return line associated with the bus, wherein the power factor correction circuit charges the bus during a startup period at a startup charging rate and during a steady-state period at a steady-state charging rate, wherein the startup charging rate is higher than the steady-state charging rate, a bus capacitor operationally coupled to the d.c. bus and return line of the power factor correction circuit, and at least one inverter operationally coupled to the d.c. bus and return line of the power factor correction circuit.
In another embodiment of the invention, a power factor correction circuit for a ballast circuit comprises, a power factor controller with an input signal and an output signal, a semiconductor switch operationally coupled to the output signal of the power factor controller, a selectively alterable impedance network operationally coupled to an output of the semiconductor switch and operationally coupled to the input signal of the power factor controller, and a impedance network control circuit operationally coupled to the impedance network.